The present invention relates to a semiconductor memory device having a layout pattern adjusted input terminal capacitance of an address input terminal or an control input terminal, for example a row address strobe (RAS) or a column address strobe (CAS).
In a semiconductor memory device such as a DRAM and the like, up to now, it has been thought that an input terminal capacitance is preferably small since a large input terminal capacitance causes a signal inputted from the outside to be delayed or to increase a charging and discharging current. Due to this, in a semiconductor memory device, the maximum standard of an input terminal capacitance is prescribed and such a semiconductor memory device is designed so that its input terminal capacitance does not exceed the maximum standard.
Up to now, as a semiconductor device of this kind which has been designed so that its input terminal capacitance does not exceed the maximum standard, Japanese Patent Laid-Open Publication No.Hei 3-116773 has disclosed a semiconductor device as shown in FIG. 5. This conventional semiconductor device is provided with a plurality of input pads for a single input signal so that the same chip can be formed into any of plural different packages. In FIG. 5, numbers 20a and 20b are input terminals, 21 is a fuse circuit, 22 is an aluminum wiring and 23 is a semiconductor substrate. A semiconductor device shown in FIG. 5 can be assembled into either of packages different in their lead positions by applying a bonding process onto the input terminal 20a in case of forming a dual inline package (DIP) and onto the input terminal 20b in case of forming a small outline package (SOP). Moreover, in the semiconductor device shown in FIG. 5, a fuse circuit 21 is provided in the course of an aluminum wiring 22 to connect each of the input pads 20a and 20b to an input protection circuit, and it is disclosed to reduce an input terminal capacitance by cutting off the fuse circuit 21 provided at an unused input pad. For example, in case of assembling the semiconductor device into a DIP package using the input pad 20a, the fuse of a fuse circuit connected with the input pad 20b is cut off by a laser. On the other hand, in case of assembling the semiconductor device into an SOP package using the input pad 20b, the fuse of a fuse circuit connected with the input pad 20a is cut off by a laser. In such a manner, FIG. 5 discloses a semiconductor device reducing its input terminal capacitance by providing a fuse circuit for each of plural input pads to be connected with a single input signal and disconnecting an unused input pad by cutting off its fuse.
As shown in the above-mentioned prior art, in a semiconductor device such as a semiconductor memory and the like, it has been thought that a smaller input terminal capacitance is better, but variation in capacitance of it has been little considered. However, with the speedup of semiconductor memory devices variations in capacitance of input terminals have come to influence their high-speed performance. When the respective input terminals vary in their input terminal capacitance, the skew characteristic is deteriorated. Particularly, in a recent high-speed DRAM such as a synchronous DRAM, a rambus DRAM and the like, small variations in input terminal capacitance of an address input terminal or a control input terminal, for example a row address strobe (RAS), a column address strobe (CAS) and so forth, have come to influence their high-speed performance.
Even the same semiconductor memory chip may be changed in input terminal capacitance and be influenced in its performance, depending upon the kind of a package to be assembled, its sealing resin and the like.